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Cadence培訓(xùn)高級班將首先讓您了解CB板上出現(xiàn)的信號反射、串擾、電源/地平面干擾以及時序匹配以等一系列問題產(chǎn)生的機理，并掌握其解決方法；然后講解并上機練習(xí)Cadence的高速 PCB設(shè)計與仿真工具的使用。使您在硬件設(shè)計過程中，能夠達到“設(shè)計即正確”的目的。

        在工作實踐中遇到了高速數(shù)字電路與高速PCB設(shè)計問題；對高速PCB設(shè)計感興趣的硬件工程師；已經(jīng)具備一定的硬件開發(fā)經(jīng)驗，需要增加就業(yè)競爭力的在校碩士及博士研究生；具備非常扎實的電子工程基本知識，并積累了相當程度的硬件工程師工作經(jīng)驗的在校本科生。

        為了保證培訓(xùn)效果，增加互動環(huán)節(jié)，我們堅持小班授課，每期報名人數(shù)限3到5人，多余人員安排到下一期進行。注意：本課程一旦開課不予退費。

        1、培訓(xùn)過程中，如有部分內(nèi)容理解不透或消化不好，可免費在以后培訓(xùn)班中重聽；
        2、培訓(xùn)結(jié)束后免費提供一個月的技術(shù)支持，充分保證培訓(xùn)后出效果；
        3、培訓(xùn)合格學(xué)員可享受免費推薦就業(yè)機會。

◆【趙老師】

有9年的FPGA和DSP系統(tǒng)硬件開發(fā)經(jīng)驗,5年視頻和圖像處理領(lǐng)域的高速DSP系統(tǒng)硬、軟件和FPGA系統(tǒng)的設(shè)計和開發(fā)經(jīng)驗，高速系統(tǒng)設(shè)計經(jīng)驗非常豐富，精通Allegro cadence和candence SPECCTRAQuest等信號完整性仿真，精通高速PCB SI仿真工具以及PADS,Altium Designer等PCB設(shè)計工具。
      
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第一階段

1 高速PCB設(shè)計中的理論基礎(chǔ)
    傳輸理論、信號完整性等等。
2 SPECCTRAQuest設(shè)計流程
    2.1 Pre-Placement
    2.2 Board Setup Requirements for Extracting and Applying Topologies
    2.3 Database Setup Advisor
        —Cross-Section
        —DC Nets
        —DC Voltages
        —Device Setup . ??—SI Models
        —SI Audit

3 拓撲結(jié)構(gòu)的抽取與仿真 Extracting and Simulating Topologies
    3.1 Pre-Route Extraction Setup—Default Model Selection.
    3.2 Pre-Route Extraction Setup—Unrouted Interconnect
    3.3 Pre-Route Template Extraction
    3.4 SQ Signal Explorer Expert
    3.5 Analysis Preferences
    3.6 SigWave

第二階段

4 確定和施加約束 Determining and Adding ConstraintsSolution
    4.1 Solution SpaceAnalysis: Step 1 to 6
    4.2 Parametric Sweeps.
    4.3 Constraints :
        Topology Template Constraints
        Switch/Settle Constraints
        Assigning the Prop Delay Constraints
        Impedance Constraint
        Diff Pair Constraints
        Wiring Constraint
        User-Defined Constraint
        Signal Integrity Constraints
    4.4 Usage of Constraints

5 模板應(yīng)用和基于約束的布局
    Template Applications and Constraint-Driven Placement
    5.1 Creating a Topology
    5.2 Wiring the Topology
    5.3 TLines and Trace Models
    5.4 Coupled Traces
    5.6 Crosstalk Simulation in SQ Signal Explorer Expert
    5.7 Simulating with Coupled-Trace Models
    5.8 Sweep Simulation Results with Coupled-Trace Models
    5.9 Extracting a Topology Using the Constraint Manager
    5.10 Electrical Constraint Set
    5.11 Applying Electrical CSet
    5.12 Worksheet Analysis
    5.13 Spacing and Physical Rule Sets
    5.14 Electrical Rule Set

第三階段

6 基于約束的布線 Constraint-Driven Routing
    6.1 Manual Routing
    6.2 Routing with the SPECCTRA Smart Route
    6.3 Driving Constraints in Routing
7 布線后的DRC檢查和分析 Post-Route DRC and Analysis
    7.1 Post-Route Analysis
    7.2 SigNoise
    7.3 Reflection Simulation
    7.4 Reflection Waveform Analysis
    7.5 Comprehensive Simulation
    7.6 Crosstalk Simulation
    7.7 Crosstalk Analysis
    7.8 Simultaneous Switching Noise Simulation
    7.9 SSN Waveform Analysis
    7.10 System-Level Analysis
    7.11 A Complete Design Link
    7.12 Initialize Design Link

8 差分信號設(shè)計 Differential Pair Design Exploration
    8.1 Types of Differential Pairs in SPECCTRAQuest
    8.2 Create Differential Pair Using SPECCTRAQuest
    8.3 Create Differential Pair Using Constraint Manager
    8.4 Assigning Differential Pair Signal Models
    8.5 Preference to Extract Unrouted Differential Pair Topology
    8.6 Extracting Unrouted Differential Pair Topology
    8.7 Custom Stimulus to Analyze Differential Pair Topology
    8.8 Differential Pair Topology Analysis
    8.9 Coupled Trace Model and Differential Pair Topology
    8.10 Layout Cross-section Editor
    8.11 Differential Pair Constraints
    8.12 Differential Pair Constraints in the Constraint Manager
    8.13 Differential Pair Analysis in the Constraint Manager

9 時序仿真和和PI仿真
9.1 時序仿真
9.2 PI仿真